1. Field of the Invention
This invention relates generally to voltage controlled oscillators, and more particularly to a method of time dithering a fully digitally-controlled oscillator (DCO) tuning input.
2. Description of the Prior Art
Operating clock rates of modem VLSI circuits, such as microprocessors and digital signal processors (DSPs), have increased greatly over recent years. These clock rates, now up to on the order of GHz, and the corresponding increase in the number of operations that can be performed over time by the VLSI circuits, have provided dramatic increases in the functionality of electronic computing systems, including mobile, battery-powered, systems such as notebook computers, wireless telephones, and the like. In order to provide such high speed functionality, functions such as on-chip clock generation and clock recovery (i.e., generation of timing information from serial bitstreams) must of course operate at these high frequencies.
As related to clock generation, the increase in clock frequencies has in turn made the timing constraints for communication among the various integrated circuits more stringent. Particularly in systems that utilize synchronous operation and data communication among multiple integrated circuits, the timing skew between external system clocks and the internal clocks that control the operation of the integrated must be reduced to very small margins.
Conventional systems generally utilize analog PLLs for on-chip generation and synchronization of internal clock signals from system reference clocks. Typical analog PLLs include a phase detector that compares the phase relationship of the reference clock to an internal clock, a charge pump and loop filter for setting an analog voltage corresponding to this phase relationship, and a voltage-controlled oscillator (VCO) for generating an output clock signal in response to the analog voltage from the charge pump and loop filter. In recent years, digital phase detectors have been used in on-chip PLLs in combination with the analog charge pump and filter, and the analog VCO; such PLLs have been referred to as xe2x80x9cdigitalxe2x80x9d, but of course in reality these PLLs are hybrid digital and analog circuits.
Recently, efforts have been made toward the development of fully digital PLLs. In combination with a digital phase detector, fully digital PLLs include a digital loop filter instead of the traditional analog filter, and include a digitally-controlled oscillator instead of the voltage-controlled oscillator. In theory, these fully digital PLLs have several advantages over their analog counterparts. First, digital logic exhibits much better noise immunity than analog circuitry. Second, analog components are vulnerable to DC offset and drift phenomena that are not present in equivalent digital implementations. Further, the loop dynamics of analog PLLs are quite sensitive to process technology scaling; whereas the behavior of digital logic remains unchanged with scaling. This requires much more significant redesign effort to migrate analog PLLs to a new technology node than is required for digital PLLs.
Moreover, power dissipation is of extreme concern for portable, battery-powered, computing systems, as power dissipation relates directly to battery life. As a result, many manufacturers are reducing the power supply voltage requirements of the integrated circuits, particularly those that are specially adapted for portable computing systems, to reduce the power consumed by these devices. It has been observed however, that a reduction in the power supply voltage applied to analog circuitry, such as analog or hybrid PLLs, does not necessarily reduce the power dissipated by these circuits; in some cases, aggressive voltage scaling has been observed to increase the power dissipated by analog circuits. Additionally, reduction in the power supply voltage to analog circuits renders the design of robust circuits much more difficult, given the reduced available xe2x80x9cheadroomxe2x80x9d for the circuits.
In view of the foregoing, PLLs in which digital techniques are used in not only the phase detector, but also in the loop filter and the controllable oscillator, are very attractive to designers. In particular, and as noted above, the implementation of fully digital PLLs to include a digitally-controlled oscillator (DCO), which is an oscillator that operates at a frequency controlled by the value of a digital control word applied thereto, has become especially attractive.
As is known in the art, high frequency circuits other than clock generation circuits also may benefit from the implementation of an all-digital PLL. For example, as noted above, the function of clock recovery (i.e., the extraction of timing information and synchronization from a serial bitstream) is common in effecting high-frequency data communication among integrated circuits and systems. It is, of course, desirable to communicate data at as high a frequency as possible, and as such the frequencies at which clock recovery circuitry are to operate are ever-increasing. Further, considering that communication is a primary function in many battery-powered systems, such as wireless telephones, wireless modems in portable computers, and the like, it is desirable to reduce power dissipation and, consequently, the supply voltage required to implement clock recovery circuits, along with increasing the frequency of operation thereof. As such, many of the advantages provided by fully digital PLLs and the DCOs associated therewith are also beneficial to clock recovery circuits, as well as other applications in modem integrated circuits. The utility of the DCO however, is not limited to PLL applications. In fact, it is contemplated that any application requiring a frequency-programmable oscillator has the potential to benefit from an efficient implementation of a DCO.
The fundamental function of a DCO is to provide an output waveform that has a frequency of oscillation fDCO that is a function of a binary-weighted digital input word D, as follows:
fDCO=f(D)=f(dnxe2x88x921xc2x72nxe2x88x921+dnxe2x88x922xc2x72nxe2x88x922+ . . . +d1xc2x721+d0xc2x720) 
Typically, the DCO transfer function f( . . . ) is defined so that either the frequency fDCO or the period of oscillation TDCO is linear with D, generally with an offset. A DCO transfer function, for example, that is linear in frequency is typically expressed as:
f(D)=foffset+Dxc2x7fstep 
where foffset is a constant offset frequency and fstep is the frequency quantization step. Similarly, a DCO transfer function that is linear in period is typically expressed as
T(D)=1/f(D)≈Toffsetxe2x88x92Dxc2x7Tstep 
where Toffset is a constant offset period and Tstep is the period quantization step. It is of course evident that, since the DCO period T(D) is a function of a quantized digital input D, the DCO cannot generate a continuous range of frequencies, but rather produces a finite number of discrete frequencies.
One common type of conventional DCO includes a high-frequency oscillator in combination with a dynamically programmable frequency divider. An example of this type of DCO is illustrated in FIG. 1a. In this example, programmable frequency divider 2 receives an n-bit digital word D which indicates the divisor value at which the frequency of the output signal HFCLK of high-frequency oscillator 4 is to be divided in generating the DCO output signal CLK. In this conventional arrangement, the period quantization step Tstep, and thus the lower bound of the timing jitter, is limited to the period of high-frequency oscillator 4. Low jitter operation thus requires oscillator 4 to operate at an extremely high frequency; for example, a 0.2 nsec step between periods requires high frequency oscillator 4 and programmable counter 2 to operate at 5 GHz.
Because of this limitation, other conventional DCO approaches directly synthesize a signal, rather than dividing down from a high frequency source. One example of a conventional direct-synthesis DCO is illustrated in FIG. 1b, which is arranged as a variable length ring oscillator. In this example, 2n delay stages 6 are connected in series, with lowest order stage 60 being an inverting stage and driving the output signal on line CLK. Decoder 8 decodes n-bit digital control word D in 2n control lines, each of which are operable to short out a corresponding stage 6, and one of which is asserted in response to the value of the digital control word D. The period of oscillation T is thus twice the sum of the delays of those delay stages 6 within the ring. For example, if the delay through each stage 6 is T6, in the case where D=0 such that only stage 60 is in the ring, the period of oscillation T will equal 2T6; in the case where D=2nxe2x88x921 (D is at its maximum), the period of oscillation T will equal 2(2n)T6, as all 2n stages 6 will be connected in the ring. In this conventional approach, the period quantization step (which sets a lower bound on the jitter) is thus 2T6 or twice the propagation delay of stage 6, which is typically an improvement over that of the conventional DCO of FIG. 1a, but which still may be too course for many applications. However, the integrated circuit chip area required for realization of the variable delay ring oscillator of FIG. 1b is substantial, considering that the number of stages 6 is exponential with the number of bits in the control word D and that typical delay stages can be quite complex, with some reported implementations requiring more than twenty transistors per stage. Further, the complexity of decoder 8 is also exponential with n, itself requiring on the order of (n+6)2n unit-size transistors. The total complexity of the circuit is therefore relatively large, resulting in a chip area that varies with n by on the order of (n+30)2n. Accordingly, a high resolution DCO constructed in this fashion can occupy a tremendous amount of chip area.
Another known approach to implementation of a digital PLL is described in J. Dunning et al., xe2x80x9cAn All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessorsxe2x80x9d, J. Solid State Circ. (IEEE, April 1995), pp. 412-422. According to this conventional approach, the desired output frequency is directly synthesized through the operation of an eight-stage current-starved ring oscillator, one such stage illustrated in FIG. 1c, where each inverting delay stage includes a pull-up leg of parallel binary-weighted transistors 9, and a pull-down leg of parallel binary-weighted transistors 11. Each transistor 9I, 11I is turned on by a corresponding bit dI (or its complement) of the control word d; switching transistors 9I, 11I are controlled by the state of line IN, and drive line OUT at their common drain node. While acceptable frequency resolution is provided according to this approach, the amount of integrated circuit chip area required for implementation of this PLL is extremely large. Since NMOS transistor 11I weighted by a factor of 2i is generally realized as 2i minimum-size transistors 110 in parallel, the number of unit-size NMOS transistors 110 in a delay stage such as shown in FIG. 1c is 2(2n)xe2x88x921. Assuming a PMOS transistor 9 to be twice the size of its corresponding NMOS transistors 11, the total number of unit-size transistors required to realize the delay stage of FIG. 1c may be considered as:
2(2n)xe2x88x921+2[2(2n)xe2x88x921]=6(2n)xe2x88x923 
For a DCO of this construction having eight delay stages, the area required for implementation will therefore vary with n by on the order of 48(2n).
By way of further background, another example of a conventional digitally-controlled oscillator is described in F. Lu, H. Samueli, J. Yuan, and C. Svensson, xe2x80x9cA 700-MHz 24-b Pipelined Accumulator in 1.2-xcexcm CMOS for Applications as a Numerically Controlled Oscillatorxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 28, No. 8 (IEEE, August 1993), pp. 878-886.
One DCO implemented to overcome the disadvantages described above in association with conventional digitally-controlled oscillators known in the art is disclosed in U.S. Pat. No. 6,028,488, entitled Digitally-controlled oscillator with switched-capacitor frequency selection, issued Feb. 22, 2000 to Landman, et al. The DCO disclosed in the ""488 patent is realized by way of a switched-capacitor array that loads a driver within the oscillator. The switched-capacitor array includes a binary-weighted set of capacitors, each of which has its capacitance controlled by one bit of a digital control word from a digital loop filter. The step size between adjacent oscillation periods, and thus the jitter, is defined by the capacitance of the least significant capacitor (corresponding to the LSB of the control word) in combination with the strength of the driver.
Digitally-controlled oscillators that employ fully digital phase-locked loops (PLLs) of type I (i.e., only one integrating pole due to the DCO frequency-to-phase conversion) generally feature faster dynamics and are used where fast frequency/phase acquisition is required or direct transmit modulation is used. Unlike in type II PLL loops however, where the steady-state phase error goes to zero in face of a constant frequency offset (i.e., frequency deviation between the actual and center DCO frequencies), the phase error in type I PLL loops is proportional to the frequency offset. Although loop dynamics can be improved through elimination of loop filtering, this leads to the increase in the so-called reference feedthrough in which the phase detector update events get transferred and frequency-modulate the DCO output. This shows itself as the spurious tones at the RF output.
In view of the foregoing, it is desirable and necessary to provide a method of time dithering a digitally-controlled oscillator (DCO) tuning control word input in order to substantially eliminate frequency modulation of the DCO output in response to phase detector update events in such a way that spurious tones can be substantially eradicated at the DCO RF output.
In one aspect of the invention, a DCO is therefore provided that can operate at low power supply voltages while substantially eliminating spurious tones at the RF output.
In still another aspect of the invention, a DCO is further provided that operates with extremely low levels of jitter while substantially eliminating spurious tones at the RF output.
In yet another aspect of the invention, a DCO is also provided that requires a relatively modest amount of chip area relative to conventional DCO circuits while still capable of substantially eliminating spurious tones at the RF output.
In yet another aspect of the invention, a DCO is provided that can function in association with a digital phase-locked loop (PLL) to substantially eliminate spurious tones at the RF output.
In yet another aspect of the invention, a DCO is provided that has significantly smaller oscillator phase noise than that generated by known DCOs that employ a delayed feedback using a variable load, such that spurious tones at the RF output are substantially eliminated.
In still another aspect of the invention, a DCO is provided that operates with substantially any negative resistance feedback source (Colpitts oscillator, gun diode, and the like) to achieve stable oscillation in a manner that substantially eliminates spurious tones at the RF output.
In still another aspect of the invention, a DCO is provided that accommodates the modulation and channel selection requirements associated with the xe2x80x9cBLUETOOTHxe2x80x9d standard while substantially eliminating spurious tones at the RF output.
A digitally-controlled oscillator according to one embodiment may be constructed as an LC tank oscillator (i.e., digitally-tunable tank circuit), where the resonant frequency inside the oscillator is changed. The LC tank oscillator is a resonator that is formulated from virtually any negative resistance source (e.g., Colpitts oscillator, gun diode, and the like) to bring the resonator to a stable oscillation. A binary-weighted capacitor bank is employed in association with a small bank of unity minimum size capacitors that are switched fast between two states to dither or modulate (similar to dithering as used in conventional D/A converters, except the present dithering is digital-to-frequency conversion rather than digital-to-analog conversion) the LSB(s) and use the Q of the digitally-tunable tank circuit as a low pass function. A DCO that uses such a tank circuit has significantly reduced phase noise when compared with conventional DCOs in which the feedback is delayed using a variable load, since the tank circuit of the present invention can be designed with a high Q. The DCO is therefore realized using an LC tank circuit in which the frequency resolution can be adjusted in such a way as to accommodate both modulation and channel selection requirements necessary to achieve xe2x80x9cBLUETOOTHxe2x80x9d RF communication otherwise not achievable using other known DCO architectures. As used herein, RF means any frequency that can be communicated over the communications medium that is being utilized.
According to one embodiment of the present invention, a time dithering scheme suitable for use with the foregoing DCO is illustrated in Figures. The tuning control word is a digital word and is synchronous to the compare frequency of the phase detector. The tuning control word would normally be connected to the digitally-controlled oscillator input through a gain stage if a loop filter is not used, such as illustrated in the phase-domain all-digital synchronous PLL synthesizer shown in FIG. 3. An accurate discrete time dithering of the tuning control word is obtained by reclocking it by the high-frequency oversampling clock and passing it through a delay shift register. A multibit input multiplexer synchronously selects the appropriate output of the delay register chain. This technique provides a means of dynamically offsetting the actual DCO update timing, which is done at the frequency reference rate, discretely by the oversampling clock. The digitized RF output of the synthesizer would be used as the high-frequency oversampling clock directly or after an appropriate frequency division, for example, by an edge-divider such as depicted in FIG. 14. The DCO may receive a digital input word from a digital PLL in a manner such as disclosed in U.S. patent application Ser. No. 09/603,023, entitled Digital Phase-Domain PLL Frequency Synthesizer, docket no. TI-30677, by Robert B. Staszewski and Dirk Leipold, filed Jun. 26, 2000, and that is incorporated by reference herein in its entirety.